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RFP25N05L
Data Sheet July 1999 File Number
2270.3
25A, 50V, 0.047 Ohm, Logic Level, N-Channel Power MOSFET
The RFP25N05L is an N-Channel logic level power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. The RFP25N05L was designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. Formerly developmental type TA09871.
Features
* 25A, 50V * rDS(ON) = 0.047 * UIS SOA Rating Curve (Single Pulse) * Design Optimized for 5V Gate Drives * Can be Driven Directly from CMOS, NMOS, TTL Circuits * Compatible with Automotive Drive Requirements * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Majority Carrier Device * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFP25N05L NOTE: PACKAGE TO-220AB BRAND RFP25N05L
Symbol
D
When ordering, include the entire part number.
G
S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
RFP25N05L
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFP25N05L 50 50 25 65 Refer to UIS SOA Curve 10 60 0.48 -55 to 150 300 260 UNITS V V A A V W W/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Single Pulse Avalanche Energy Rating (See Figures 4, 15, and 16). . . . . . . . . . . . . . . . . . . . . . Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 125oC.
Electrical Specifications
PARAMETER
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IGSS IDSS TEST CONDITIONS VGS = 0V, ID = 250A (Figure 10) VGS = VDS, ID = 250A (Figure 9) VGS = 10V, VDS = 0V VDS = 40V, VGS = 0V TC = 150oC MIN 50 1.0 (Figures 7, 8) VGS = 0 - 10V VGS = 0 - 5V VGS = 0 - 1V VDD = 40V, ID = 25A, RL = 1.6 (Figures 17, 18) TYP 15 35 40 14 MAX 2.0 100 1.0 50 0.047 0.056 60 100 80 45 3.0 2.083 80 UNITS V V nA A A ns ns ns ns ns ns nC nC nC
oC/W oC/W
Drain to Source Breakdown Voltage Gate to Threshold Voltage Gate to Source Leakage Zero Gate Voltage Drain Current
Drain to Source On Resistance (Note 2)
rDS(ON)
VGS = 5V, ID = 25A VGS = 4V, ID = 25A
Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge (Gate to Source + Gate to Drain) Gate Charge at 5V Threshold Gate Charge Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
t(ON) td(ON) tr td(OFF) tf t(OFF) Qg(TOT) Qg(5) Qg(TH) RJC RJA
VDD = 25V, ID =12.5A RL = 2, RGS = 5 (Figures 15, 16)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Diode Reverse Recovery Time NOTES: 2. Pulse Test: Pulse width 80s, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. SYMBOL VSD trr ISD = 25A ISD = 25A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns
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RFP25N05L Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 50 100 150 20
Unless Otherwise Specified
30
0.8 0.6 0.4 0.2 0
10
0 25 50 TC, CASE TEMPERATURE (oC) 75 100 125 TC , CASE TEMPERATURE (oC) 150
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
102 ID MAX CONTINUOUS ID, DRAIN CURRENT (A) 10 OPERATION IN THIS AREA LIMITED BY rDS(ON) 1
TJ = MAX RATED, TC = 25oC IAS, AVALANCHE CURRENT (A)
102 Idm
STARTING TJ = 25oC STARTING TJ = 150oC
10
DC
If R = 0 tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3 RATED BVDSS - VDD) +1] 1 0.01 0.10 1 tAV, TIME IN AVALANCHE (ms)
VDSS (MAX) = 50V 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 102
10
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA (SINGLE PULSE UIS SOA)
IDS, DRAIN TO SOURCE CURRENT (A)
10V
5.0V
TC = 25oC VGS = 4.0V
IDS(ON), DRAIN TO SOURCE CURRENT (A)
65 55 45 35 25 15 5 0
65 55 45 35 25 15 5 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) 7.5 VDS = 15V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
3.0V
2.0V 6.0 1.5 3.0 4.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 7.5
FIGURE 5. SATURATION CHARACTERISTICS
FIGURE 6. TRANSFER CHARACTERISTICS
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RFP25N05L Typical Performance Curves
1.4 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s 1.3 DUTY CYCLE = 0.5% MAX ID = 25A 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 4 5 6 VGS, GATE TO SOURCE VOLTAGE (V) 7
Unless Otherwise Specified (Continued)
2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
2.0
ID = 25A, VGS = 5V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
1.5
1.0
0.5
0 -50
0
50
100
150
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
1.4 1.3 NORMALIZED GATE TO THRESHOLD VOLTAGE 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 0 50 100 150 200
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
1.4 ID = 250A NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2
ID = 250A VGS = VDS
1.0
0.8
0.6
0 -50
0
50
100
150
200
TJ, JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED GATE TO THRESHOLD vs JUNCTION TEMPERATURE
2000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
50 10 VGS , GATE TO SOURCE VOLTAGE (V) RL = 2, VGS = 5V IG(REF) = 0.60mA PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS V = 0.75 BV VDD = BVDSS VDD = 0.50 BVDSS VDD = BVDSS DD DSS VDD = 0.25 BVDSS GATE SOURCE VOLTAGE
1600 C, CAPACITANCE (pF)
VDS , DRAIN TO SOURCE VOLTAGE (V)
37.5
8
1200 CISS 800
6
25
4
12.5 2 DRAIN SOURCE VOLTAGE 0 0 I G ( REF ) 20 -----------------------I G ( ACT ) t, TIME (s) I G ( REF ) 80 -----------------------I G ( ACT )
400
COSS CRSS
0
0
5
10
15
20
25
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 11. CAPACITANCE vs VOLTAGE FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
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RFP25N05L Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 15. SWITCHING TIME TEST CIRCUIT
FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
CURRENT REGULATOR
VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS
12V BATTERY
0.2F
50k 0.3F
G
DUT 0
Ig(REF) 0 IG CURRENT SAMPLING RESISTOR
S VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0
FIGURE 17. GATE CHARGE TEST CIRCUIT
FIGURE 18. GATE CHARGE WAVEFORMS
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RFP25N05L
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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